The present invention relates to a semiconductor memory, for example, of the type utilized in a dynamic RAM (random access memory).
A memory cell of one bit in a dynamic RAM comprises a MOSFET type memory cell, i.e., a data storage capacitor and an address selecting MOSFET, and data of logic "1", "0" is stored in form of charge in the capacitor. Reading of data is performed in that the MOSFET is rendered on and the capacitor is connected to a data line, and how the potential of the data line varies corresponding to the charge stored in the capacitor is sensed using the reference potential. The capacitor utilized here is a MIS (metal insulator semiconductor) capacitor between a gate electrode and a channel. Fixed potential is supplied steadily to the gate electrode. A system of supplying voltage 1/2 Vcc, i.e. a falf of the source voltage Vcc, to the gate electrode of the MIS capacitor of the memory cell is disclosed, for example, in U.S. patent application Ser. No. 530,079, filed on Sep. 7, 1983. One system of forming the read reference potential of the memory cell is a half precharge system of the data line (or dummy cell-less system), for example, disclosed in ISSCC DIGEST OF TECHNICAL PAPERS, 1984, p 276-p 277 or "Nikkei Electronics" p 243-p 263, published on Feb. 11, 1985 by Nikkei McGraw-Hill, Inc.